A memory chip generally comprises a plurality of memory elements that are deposited onto a silicon wafer and addressable via an array of column conducting leads (bit lines) and row conducting leads (word lines). Typically, a memory element is situated at the intersection of a bit line and a word line. The memory elements are controlled by specialized circuits that perform functions such as identifying rows and columns from which data are read or to which data are written. Typically, each memory element stores data in the form of a “1” or a “0,” representing a bit of data.
An array of magnetic memory elements can be referred to as a magnetic random access memory or MRAM. MRAM is generally nonvolatile memory (i.e., a solid state chip that retains data when power is turned off). FIG. 1 illustrates an exemplary magnetic memory element 100 of a MRAM in the related art. The magnetic memory element 100 includes a data layer 110 and a reference layer 130, separated from each other by at least one intermediate layer 120. The data layer 110 may also be referred to as a bit layer, a storage layer, or a sense layer. In a magnetic memory element, a bit of data (e.g., a “1” or “0”) may be stored by “writing” into the data layer 110 via one or more conducting leads (e.g., a bit line and a word line). A typical data layer 110 might be made of one or more ferromagnetic materials. The write operation is typically accomplished via write currents that create two external magnetic fields that, when combined, set the orientation of the magnetic moment in the data layer to a predetermined direction.
Once written, the stored bit of data may be read by providing a read current through one or more conducting leads (e.g., a read line) to the magnetic memory element. For each memory element, the orientations of the magnetic moments of the data layer 110 and the reference layer 130 are either parallel (in the same direction) or anti-parallel (in different directions) to each other. The degree of parallelism affects the resistance of the element, and this resistance can be determined by sensing (e.g., via a sense amplifier) an output current or voltage produced by the memory element in response to the read current.
More specifically, if the magnetic moments are parallel, the resistance determined based on the output current is of a first relative value (e.g., relatively low). If the magnetic moments are anti-parallel, the resistance determined is of a second relative value (e.g., relatively high). The relative values of the two states (i.e., parallel and anti-parallel) are typically different enough to be sensed distinctly. A “1” or a “0” may be assigned to the respective relative resistance values depending on design specification.
The intermediate layer 120, which may also be referred to as a spacer layer, may comprise insulating material (e.g., dielectric), non-magnetic conductive material, and/or other known materials.
The layers described above and their respective characteristics are typical of magnetic memory elements based on tunneling magnetoresistance (TMR) effects known in the art. Other combinations of layers and characteristics may also be used to make magnetic memory elements based on TMR effects.
Still other configurations of magnetic memory elements are based on other well known physical effects (e.g., giant magnetoresistance (GMR), anisotropic magnetoresistance (AMR), colossal magnetoresistance (CMR), and/or other physical effects).
Throughout this application, various exemplary embodiments will be described in reference to the TMR memory elements as first described above. Those skilled in the art will readily appreciate that the exemplary embodiments may also be implemented with other types of magnetic memory elements known in the art (e.g., other types of TMR memory elements, GMR memory elements, AMR memory elements, CMR memory elements, etc.) according to the requirements of a particular implementation.
The various conducting leads (e.g., bit lines, word lines, and read lines) which are used to select the memory elements in a MRAM, and to read data from or write data to the memory elements are provided by one or more additional layers, called conducting layer(s). FIG. 2 illustrates an exemplary memory array 200 including magnetic memory elements 100a–100d that are selectable by bit lines 210a–210b, word lines 220a–220b, and read lines (not shown) during read or write operations. Magnetic memory elements 100a–100d are generally located at the cross-points of the bit lines 210a–210b and word lines 220a–220b. 
The read lines may be located on top of or beneath (and insulated from) the bit lines 210a–210b or the word lines 220a–220b, or any other suitable configuration according to a particular implementation.
Conventional magnetic memory elements as described above may be written when currents in the bit line and word line intersecting at a selected memory element generate enough combined magnetic fields to switch the magnetic orientation of the data layer of the selected memory element. It is known that when a magnetic memory element is heated (e.g., to a temperature higher than room temperature), the magnetic orientation of the data layer can be more easily switched (e.g., by a smaller combined magnetic field). Thus, thermally assisting switching of magnetic orientations in memory elements is often a desirable feature.
Thermal-assistance is typically provided by additional heater structures contacting or nearby the memory elements. These heater structures are typically formed for the sole purpose of heating its proximate memory element. Forming additional heater structures, however, incurs additional fabrication costs.
Thus, a market exists for an alternative method to heat memory elements without necessarily forming additional heater structures.